University of Michigan (U-M) researchers have developed an ultra low power microchip which 'uses 30,000 times less power in sleep mode and 10 times less in active mode than comparable chips now on the market.' It only consumes 30 picowatts in sleep mode, which means that a simple watch battery could power the chip for more than 200 years. Of course, this is not a processor for your next computer. It is designed for sensor-based devices such as medical implants, environment monitors or surveillance equipment. However, the design is very clever. But read more...
You can see above a die photo of the Phoenix Processor. (Credit: University of Michigan)
This project has been led by Scott Hanson and Mingoo Seok, two doctoral students in the U-M Department of Electrical Engineering and Computer Science (EECS.) They were supervised by professors David Blaauw and Dennis Sylvester, in charge of the VLSI Design/Automation Lab.
So how did these scientists build this very efficient chip? The answer is extremely simple: they've reduced the battery size. "Phoenix is the same size as its thin-film battery, marking a major achievement. In most cases, batteries are much larger than the processors they power, drastically expanding the size and cost of the entire system, said David Blaauw, a professor in the Department of Electrical Engineering and Computer Science. For instance, the battery in a laptop computer is about 5,000 times larger than the processor and it provides only a few hours of power."
The other great idea behind this design was to concentrate on the sleep mode of the chip. "Phoenix engineers focused on sleep mode, where sensors can spend more than 99 percent of their lives. Sensors wake only briefly to compute at regular intervals. 'Sleep mode power dominates in sensors, so we designed this device from the ground up with an efficient sleep mode as the No. 1 goal. That's not been done before,' said Dennis Sylvester."
In fact, the Phoenix processor is set to work in sleep mode by default. "A low-power timer acts as an alarm clock on perpetual snooze, waking Phoenix every ten minutes for 1/10th of a second to run a set of 2,000 instructions. The list includes checking the sensor for new data, processing it, compressing it into a sort of short-hand, and storing it before going back to sleep."
This research work will be shown next week at the IEEE Symposium on VLSI Circuits (2008 VLSI Symposia), to be held in Honolulu, Hawaii, on June 17-20, 2008. It will be the subject of a presentation called "The Phoenix Processor: A 30pW Platform for Sensor Applications" during the Power-Aware Processing session. Here is the abstract. "An integrated platform for sensor applications, called the Phoenix Processor, is implemented in a carefully-selected 0.18μm process with an area of 915x915μm2, making on-die battery integration feasible. Phoenix uses a comprehensive sleep strategy with a unique power gating approach, an event-driven CPU with compact ISA, data memory compres-sion, a custom low leakage memory cell, and adaptive leakage management in data memory. Measurements show that Phoenix consumes 29.6pW in sleep mode and 2.8pJ/cycle in active mode."
For even more information, this processor was described in the 2007 Annual Report of the Engineering Research Center for Wireless Integrated MicroSystems (WIMS ERC), a partnership between the University of Michigan joined with Michigan State University and Michigan Technological University. Please jump to the Micropower Circuits section of this report (PDF format, 21 pages, 2.46 MB).
The Phoenix processor is described on page 5 of this document -- with the die photo shown above. "To meet the growing demand for pervasive computing systems, we have designed an ultra-low-power integrated platform for sensor applications, called the Phoenix Processor. Recent work has explored aggressive Vdd scaling for reducing active energy. However, the power consumed during idle periods, which can be >99% of the lifetime, dominates total power consumption. To limit sleep-mode power, Phoenix leverages a comprehensive sleep strategy using a unique power-gating approach, a CPU with compact instruction set, a custom low-leakage memory cell, adaptive leakage management in the data memory, and data-memory compression." A test chip was fabricated and has "the lowest energy consumption ever published in a system of this size."
I'm not familiar enough with the sensors world to know if this new design will have a serious impact, but I would certainly welcome batteries with longer lives for my laptops.
Sources: University of Michigan news release, June 13, 2008; and various websites
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