DARPA's $1.5 billion scheme aims to reinvent the computer chip

The Electronics Resurgence Initiative (ERI) hopes to find a way to leave silicon in the past.

The Defense Advanced Research Projects Agency (DARPA) has earmarked $1.5 billion to fund projects through a new initiative designed to find new ways to power our computers.

This week, the agency said that the Electronics Resurgence Initiative (ERI) is a scheme which will drive us towards new ways to improve general-purpose computing and now, partners have joined in their droves to develop new technological solutions.

Moore's Law has prompted the accelerated development of transistors and electronics at large; however, DARPA says this is now showing signs of slowing.

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"It has become increasingly more challenging to achieve performance gains from generalized hardware, setting the stage for a resurgence in specialized architectures," DARPA says.

To keep up the pace, the agency's five-year ERI initiative, first announced last year, has now selected research teams from academia and the technology industry to develop flexible architectures and new chip designs.

System-on-Chip (SoC) platforms are a key area in which funding is available for participants to create and test new architectures, not only to improve our current silicon-based designs but to also look for ways to reduce expense.

DARPA says the overall goal is to be a catalyst for semiconductor innovation and circuit design in the United States.

The projects under the ERI umbrella are below:

Intelligent Design of Electronic Assets (IDEA): The creation of a "no human in the loop" layout generator that would enable users with limited electronic design expertise to complete the physical design of electronic hardware within 24 hours, reducing "design times from years to a single day" for digital circuits, mixed-signal integrated circuits (IC), systems-in-package (SiP), and printed circuit boards (PCBs) development.

Posh Open Source Hardware (POSH): The creation of an open source (OS) SoC design and verification ecosystem that will enable cost-effective design processes for complicated SoCs.

Domain-specific System on Chip (DSSoC) and the Software Defined Hardware (SDH) program: Both projects seek to optimize software and hardware without complex programming.

"Both programs aim to prove that there need not be a continued tradeoff between efficiency, like that found in application-specific integrated circuits (ASICs) -- that is, hardware customized for a specific application -- and flexibility, the hallmark of general-purpose processors," the agency says.

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Three Dimensional Monolithic System-on-a-Chip (3DSoC) program: The design of vertical, rather than flat or planar microsystem components to enhance traditional silicon circuits, as well as new means of computing vast amounts of information. In addition, the project has been launched to reduce memory bottlenecks.

Foundations Required for Novel Compute (FRANC) program: The focus of this scheme is to specifically reduce memory bottlenecks through alternative means of separating memory and logic functions. The program also includes the creation of new architectures which process data in ways that eliminate or minimize data movement.

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Partners include Intel, NVIDIA, Qualcomm, the University of California, San Diego; Yale University; Northrop Grumman Mission Systems; Cadence Design Systems; Xilinx; Synopsys; the University of Southern California, and Princeton University, among many others.

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