Intel's "Tick-Tock" strategy, where each "tick" representing a die shrink was followed up by a "tock" representing a new microarchitecture, served the company well for a good decade before being replaced with a different approach in 2016.
But has Intel given up on its new strategy in order to compete against AMD's upcoming Ryzen silicon?
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Intel's new approach was a three-pronged strategy called "Process-Architecture-Optimization," and Kaby Lake chips are a product of this strategy, being an "Optimization" of the Skylake "Architecture" and the "Process" of Broadwell. The idea was that Intel could squeeze three generations of processors from a single architecture.
Or that was the plan.
But the announcement last week that Intel was going to release 8th-generation chips codenamed Coffee Lake which are based on 14-nanometer architecture, as opposed to the anticipated 10-nanomenter architecture (codenamed Cannon Lake) suggests that the "Process-Architecture-Optimization" strategy might already be abandoned as Intel reuses the architecture for a fourth time.
It's doubly interesting given that both last year and earlier this year, Intel denied rumors that the 10-nanometer architecture would be delayed. In fact, rumors that Intel was having trouble with its 10-nanometer die shrink date back to 2015.
In spite of Intel seemingly abandoning the "Process-Architecture-Optimization" strategy at the first hurdle, the new Coffee Lake chips are still expected to produce a 15 percent performance boost over its predecessor, although it is unclear whether this refers to desktop or mobile chips.
Bear in mind that Intel promised a similar jump between Skylake and Kaby Lake, and this only materialized for desktop chips, and the performance boost was down to clock speed and not instructions per clock.
While Intel is being tight-lipped about what's going on here, the broad strokes are pretty clear -- Intel needs new chips to compete against AMD's upcoming Ryzen chips, but 10-nanometer Cannon Lake silicon isn't yet ready, so Intel is forced to squeeze another iteration out of the 14-nanometer architecture.
And this might not be the last time. As the architectures get finer, making the jumps will be more difficult, and if Intel is having difficulty transitioning from 14-nanometer to 10-nanometer, future die shrinks are going to be equally -- if not more -- tricky.
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