Just two years after developing a 7nm chip with 20 billion transistors, IBM has taken the wraps off technology that will usher in smaller, 5nm chips with higher performance and greater efficiency.
IBM and its Research Alliance partners, GlobalFoundries and Samsung, announced the 5nm breakthrough today, which offers a path to delivering chips with significant improvements on today's leading 10nm chips.
IBM hopes the technology will lead to 30-billion transistor chips that are more capable of meeting tomorrow's demands for artificial intelligence, virtual reality and mobile devices.
Rather than use current FinFET or "fin field-effect transistor" architecture, IBM has been exploring stacked nanosheet transistors, aided by a technique that allows it to adjust the chip's design for improved power and performance in ways that FinFET can't.
Chips based on IBM's nanosheet 5nm technology will offer 40 percent greater performance than today's 10nm chips, or a 75 percent power savings at the same performance.
FinFET chips can scale down to 5nm but the denser transistors on that architecture doesn't boost performance because the closer fins don't provide more current flow, according to IBM.
The key to fine-tuning the nanosheet transistors is a technique called Extreme Ultraviolet (EUV) lithography, which IBM also used to create a 7nm node with 20 billion transistors two years ago.
"Using EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design," explains IBM.
"This adjustability permits the fine-tuning of performance and power for specific circuits, something not possible with today's FinFET transistor architecture production, which is limited by its current-carrying fin height."
Chip-makers are looking to EUV lithography to stave off the death of Moore's Law. GlobalFoundaries' won't be using EUV for its new 7nm FinFET process, but is ready to support it when it believes the technology is ready, probably when it begins making 5nm chips. Samsung and TSMC are also preparing for it.
The 5nm research was carried out at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering's NanoTech Complex in Albany, NY, and is detailed in a new Research Alliance paper Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET.
The group says 5nm chips will be available in the not too distant future.
The research is an important milestone in IBM Research's decade-long experiments with nanosheet semiconductors since it the first time it's been able to show a stacked nanosheet design has superior electrical properties than FinFET.
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