Amid a slew of product announcements at Intel's Developer Forum in Beijing, enterprise division head Pat Gelsinger has unveiled plans for a teraflops IA architecture code-named Larrabee. The many-core designs will be programmable using existing software tools and will be aimed at high-performance computing applications such as financial analytics and visualisation, and in vertical sectors such as health and mining.
"This will be our first many-core product," Gelsinger told ZDNet UK. "It will deliver a teraflop level of performance using an IA [Intel Architecture] compatible core. It's not some exotic new architecture, it leverages decades of investment. Designing in a parallel, many-core fashion for these applications is the right approach." Intel is not revealing any further details, such as the number of cores or bus architecture, but it says that working silicon will be demonstrated in 2008.
Intel chief technology officer Justin Ratner showed the previously announced 80-core Polaris research processor running at one and two teraflops, with clock speeds of 3.13GHz and 6.26GHz and power dissipation of 47 and 192 watts respectively.
More was revealed on the next generation of mainstream processor, code-named Penryn. This is Intel's first 45nm product and is due to debut in the second half of this year in five formats: dual-core and quad-core versions for server and desktop, and dual-core only for mobiles. An increase in server performance of the order of 25 percent for Java processing should be expected over the current generation of quad-core chips, Intel says, although no concrete benchmark figures have been released.
Also later this year, Intel plans to release Caneland, a high-end multi-processor server product based on quad-core and dual-core Xeon 7300 chips — previously known as Tigerton. This will support up to four sockets, putting 16 cores into a blade.
Intel also announced two system-on-a-chip (SOAC) devices; a network processor code-named Tolapai and the CE 2110 Media Processor. Tolapai combines an IA architecture core with packet and security management hardware, together with memory and IO controllers, to provide the major functions of many network devices in a single package. The company claims an eight-fold throughput improvement for around 20 percent less power than the equivalent four-chip design.
The CE 2110 Media Processor is intended to provide similar economies to manufacturers by combining many set-top box-style consumer electronics functions into a single IA-architecture chip.
At the Intel Developer Forum in Beijing, Pat Gelsinger unveiled plans for a teraflops IA architecture code-named Larrabee