IBM has devised materials and processes that could help improve the efficiency of chip production at the 7nm node and beyond.
The company's researchers are working on challenges in the emerging field of 'area-selective deposition', a technology that could help overcome limitations on lithographic techniques to create patterns on silicon in 7nm processes.
Semi Engineering has a neat account of lithographic patterning and why at 7nm there's growing interest in area-selective deposition.
Techniques such as 'multiple patterning' helped ensure integrated circuits kept scaling, but as chips have shrunk from 28nm to 7nm processes, chipmakers have needed to process more layers with ever-smaller features that need more precise placement on patterns.
Those features need to align between layers. When they don't, it leads to 'edge placement error' (EPE), a challenge that Intel lithography expert Yan Borodovsky believed lithography couldn't solve and which would ultimately impede Moore's Law.
In 2015 he encouraged the industry to investigate area-selective deposition, the area that IBM's researchers are exploring, which may one day be a successor to EUV lithography, the technique Samsung is now preparing for the fab after decades in the lab.
Fabs already use some forms of selective deposition to deposit materials on metal surfaces in devices. Area-selective deposition requires a tool that can deposit different combinations of material sets -- metals on metals and dielectrics on dielectrics -- on a device.
Rudy J Wojtecki, a researcher at IBM's Almaden Research Center, explains IBM's effort to improve the technology:
"With traditional methods of fabrication, this would require coating a substrate with resist, patterning the resist through an exposure step, developing the image, depositing an inorganic film and then stripping the resist to give you a patterned inorganic material.
"We found a way of depositing this inorganic film much more simply, using a self-aligned process, where we immerse a prepatterned substrate in a solution containing a special material and then add that coated substrate it to a deposition chamber and you're done. We are literally able to grow a component of a device in a controllable manner at the nanoscale."
The group is using one of three main methods for area-selective deposition called 'atomic layer deposition' with a focus on using 'self-assembled monolayers' (SAMs).
It may help pave the way for hardware that better supports AI applications, such as three-dimensional structures.
"Once we develop methods of scaling this process, we can begin to integrate it as we build next-generation hardware, whether it is for new AI hardware or making devices at the 7nm technology node or beyond," Wojtecki said.
IBM isn't alone in developing techniques for area-selective atomic layer deposition, but Wojtecki argues his ability to tailor a chemical structure for demanding applications has enabled the development of "new polymerizations, materials and characterization methods" that may one day become scalable.
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