Samsung applies 3D stacking tech on 7nm EUV chips

The technology will allow customers to design smaller and more powerful chips by stacking SRAM on top of the logic die.
Written by Cho Mu-Hyun, Contributing Writer

Samsung Electronics has successfully applied 3D stacking technology on a test chip that was made using the 7nm extreme ultraviolet (EUV) chip making process, the company said on Thursday.

Dubbed extended cube (X-Cube), Samsung used the technology to stack the SRAM on top of a logic die. This differs from the conventional method where SRAM, which is used for cache memory, is placed on the same plane next to logic chips such as CPU and GPU.

The South Korean tech giant said the technology will allow customers to design chips that take up less space.

Samsung will also apply its TSV technology in which the wires for the memory layer and the logic layer are connected through tiny holes instead of around the controller to increase speed, lower power consumption, and allow the chips to be packed in a more compact manner. 

The ultra-thin package design offered by these technologies also allow the chips to have shorter signal paths between the dies to maximise data transfer speed and energy efficiency, Samsung added.

The company will offer the design methodology and flow for X-Cube to customers so that they can start designing 7nm and 5nm chips made with the EUV process

Image: Samsung

Customers will also be able to use Samsung's fabrication lab, which the company said will result in errors being caught more quickly and reductions in development time.

The company will showcase the technology at the high-performance computing conference Hot Chips, which will be streamed between August 16 to 18.

In May, Samsung began building a new EUV foundry line for chips that are 5nm or smaller. It will begin full operations next year.

Last year, the company also announced that it would invest 133 trillion won by 2030 to strengthen its logic chip businesses. 

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