Micron says good times to continue for memory

Both DRAM and flash memory pose plenty of technology challenges. At the VLSI Symposia, Micron explained how it has overcome these hurdles and why customers will continue to demand larger and faster memory.
Written by John Morris, Contributor

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The memory industry has had a great run over the past couple of years with fewer players, high prices, and rising demand for chips in everything from phones to cloud data centers. In a talk at this year's VLSI Symposia, Micron's Scott DeBoer explained why the good times will keep rolling as chipmakers find new ways to advance technology even as traditional scaling slows -- including several more generations of DRAM over the next decade without the need for EUV lithography.

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In the PC era, memory was a commodity and the drivers were different -- the Windows refresh cycle for DRAM and USB drives and memory cards for flash memory. The memory and storage markets combined represented around $38 billion in annual sales and customers generated about 250 billion gigabytes of data each year. Thing began to accelerate in the mobile era starting with the introduction of the iPhone in 2007. The market grew to around $62 billion in revenue and users were generating 7,000 billion gigabytes per year.

Now, we are at the beginning of a new era. Micron refers to as the "data economy," though the rest of the world generally calls it the AI era. DeBoer said that AI is a "game-changer" because these workloads use six times as much DRAM and twice the solid-state storage of a standard server in a cloud data center. By last year, memory and storage had grown to a $128 billion market and the world generated 22,000 billion gigabytes of data, according to Micron's estimates.

All this is happening at a time when conventional scaling of planar memory has started to run out of steam. Nevertheless, chipmakers continue to find ways to increase density, cut costs, and maintain the performance and reliability of memory. "Traditional scaling is slowing but that's raising the bar for innovation in other ways," DeBoer said.

Three technologies have been critical for Micron, which develops and manufactures memory jointly with Intel. The use of multi-patterning has made it possible to fabricate smaller features with existing tools. Micron began using double-patterning about a decade ago to scale planar NAND features below 60nm, and it is now used in DRAM "and pretty much every memory technology" below 40nm. CMOS under the array (CuA), which as the name implies moves all the peripheral circuitry on the die directly under the memory array, is the equivalent of one full shrink, DeBoer said. Finally, Micron (and others) figured out how to stack memory arrays on top of one another to create higher density chips.

This year, Micron is rolling out its 1Ynm DRAM (translation: its second generation of DRAM technology below 20nm), and DeBoer said the company is confident that the roadmap will extend to at least three more generations beyond this ,though he admitted that cost reductions will depend on some materials and architectural innovations. DRAM scaling is "bottoming out" because of the capacitor, specifically its dielectric, or electrical insulator, and extremely high-aspect ratio.

TSMC, Samsung, GlobalFoundries, and Intel are all racing to introduce EUV lithography to manufacture logic at 7nm and below. (Samsung will be giving a presentation on its 7nm process with EUV in Honolulu later this week.) But DeBoer said that the DRAM multi-patterning is a lot more cost-effective than most people realize, and he showed data indicating double-patterning and even quadruple-patterning will be more cost effective than EUV over the next decade. "At least in this period of time, EUV doesn't make sense in the DRAM space," DeBoer said. "It's not as simple as EUV comes in and saves the day for DRAM. I know it's different for logic."

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The introduction of 3D NAND flash -- this year Micron and everyone else is starting production of 96-layer devices -- has circumvented the end of planar scaling, but 3D NAND has its own scaling challenges including the same issues with high aspect-ration etches. In addition, the challenges of maintaining nanometer-level uniformity in chips now scaling up to one terabit (125GB) is "mind-blowing."

Micron is using several techniques to mitigate these issues. Last year, it began stacking two high-yielding, 32-layer chips on top of one another to create a 64-layer device, which "really took the pressure off of the equipment suppliers for the most difficult part of 3D NAND, which is the etch through the layers." The latest third-generation 3D NAND is its second to use array stacking, combining two 48-layer chips, and the third to make use of CMOS Under the Array, resulting in what DeBoer said is the world's smallest 512Gb die.

Last month, Micron and Intel announced qualification of the industry's first 64-layer 3D NAND flash to use QLC, Quad Level Cell technology, to further increase density, as well-as a solid-state drive based on it. Toshiba/Western Digital and Samsung have also announced QLC products. DeBoer said Micron's next generation of 3D NAND will deliver a more than 30-percent increase in write bandwidth and use 40 percent less energy to help it target markets such as phones and automotive.

The annual phone refresh is now driving innovation in memory technology. Memory has grown to 26 percent of the bill of materials of an iPhone -- twice the cost of the applications processor. And new applications such as 5G wireless, high-resolution photos and videos, neural network engines, advanced user authentication, and augmented reality will continue to drive demand for larger and faster memory subsystems.

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In general, memory has failed to keep pace with CPUs in terms of cost reductions and performance improvements. The current hierarchy is dictated by capacity and latency, and it leaves a large gap between memory (SRAM and DRAM) and storage (flash-based SSDs and hard drives). The internal memory bandwidth is quite high, DeBoer said, but overall system performance is limited by the narrow bus that connects it to the processor. That gap leaves an opportunity for innovation including High-Bandwidth Memory, different ways of partitioning compute and memory, and new types of non-volatile memory altogether.

The candidates include phase-change memory, STT-MRAM, and resistive RAM (ReRAM), and there are many start-ups and memory companies working on them, but none of them appears to be a candidate for a universal memory. "These are interesting in different ways," DeBoer said. "If you look at them as a DRAM or NAND replacement, they all look bad and there are fundamental limitations to each of them."

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Micron and Intel's answer to this is 3D XPoint memory, which the companies claim is 10-times denser than DRAM and offers 1,000x the speed and endurance of NAND flash memory. But the key advantage of 3D XPoint is that it is already in production with the second-generation now introduced to manufacturing. "We like to call this emerging memory that emerged, a storage-class memory that is in volume production now and reaching higher and higher levels of capability," he said. While 3D XPoint has not yet reached its original targets for density, performance, and price, DeBoer said Micron has a good scaling roadmap and will continue to improve the technology.

The time will come when the industry needs a replacement for DRAM. But for now, Micron says the future looks bright for DRAM, flash, and 3D XPoint.

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