​Korean chip packager Nepes commercialises cheaper PLP process

Korean semiconductor packager Nepes has successfully commercialised fan-out panel-level package tech that will allow chip makers to dramatically reduce production costs.
Written by Cho Mu-Hyun, Contributing Writer

Korean semiconductor packager Nepes has become the world's first to commercialize fan-out panel level package (FO-PLP) technology.

It will allow smartphone makers to reduce costs spent on chips, which are among the priciest handset components along with displays and camera modules.

Nepes is ahead of bigger rival Samsung Electro-Mechanics, which supplies to Samsung Electronics, as well as Japanese competitor J-Device. Samsung Electro-Mechanics has scheduled launch of its PLP process for the second half of the year.

Nepes said it will apply the process for an unnamed client that supplies analogue semiconductors for smartphones, starting this month.

PLP method, compared to wafer level package (WLP), has a higher production output. WLP uses a circular wafer as substrate for the chips, which results in the circular edges being thrown away, while the rectangular PLP reduces waste.

For the unnamed client, Nepes will apply both fan-in and fan-out methods. Fan-out embeds low cost material between dies to add more input/output (IO) in the peripherals of a chip, compared to fan-in, which uses just the chip's surface.

Taiwanese TSMC was the first to apply fan-out in WLP for Apple's A10 application processor.

Nepes is the first to combine fan-out and PLP, both higher-tier technology than fan-in and WLP. The company looks to win more clients in the US, China, and Japan with the tech.

The company hopes its application will be widened to logic chips, or processors, that are being used beyond smartphones, such as tablets and automated cars.

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